Embodiments of the inventive concept described herein relate to a semiconductor memory device, and more particularly, relate to a bit line sense amplifier sensing multi-bit data stored in a memory cell, a semiconductor memory device, and a multi-bit data sensing method thereof.
As a semiconductor memory device, a volatile memory device refers to a memory device that loses data stored therein at power-off. The volatile memory device includes a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous DRAM, and the like. In contrast, a nonvolatile semiconductor memory device retains data stored therein even when power is not supplied thereto. For this reason, the nonvolatile semiconductor memory device is typically used to store information that has to be retained regardless of whether power is supplied thereto. In general, a multi-level cell (MLC) technology for storing multi-bit data in one memory cell is being applied to increase the capacity of the nonvolatile memory device.
As the demand on a high-capacity volatile memory device increases, there are attempts to store multi-bit data in one DRAM cell. However, unlike the nonvolatile memory device sensing a level of a threshold voltage, the DRAM sensing the amount of charges stored in a cell capacitor needs restoring sensed data at the same time with a sensing operation. Accordingly, there is a need to accurately control a function of a sense amplifier for the purpose of restoring charges, the amount of which corresponds to sensed multi-bit data, to the cell capacitor after sensing charges stored in the cell capacitor.
To implement a multi-level cell of the DRAM, in a sense amplifier of an open bit line structure sensitive to a small noise or offset, a structure in which a sensing and restoring operation of high reliability is possible is required.